According to the prior art, semiconductor wafers are produced in a large number of successive process steps which can generally be divided into the following groups:
a) production of a single crystal consisting of semiconductor material (crystal pulling);
b) separation of the semiconductor single crystal into individual wafers (“wafering”, “slicing”);
c) mechanical processing of the semiconductor wafers;
d) chemical processing of the semiconductor wafers;
e) chemo-mechanical processing of the semiconductor wafers;
f) thermal treatment of the semiconductor wafers and/or epitaxial coating of the semiconductor wafers.
In addition to this, there are a large number of secondary steps, such as cleaning, measuring and packaging.
A semiconductor single crystal is usually produced by pulling a single crystal out of a melt (CZ or “Czochralski” method) or by the recrystallisation of a rod of polycrystalline semiconductor material (FZ or “floating zone” method).
Wire sawing (“multi-wire slicing”, MWS) and inner diameter sawing are known as cutting methods.
In wire sawing, a plurality of semiconductor wafers is cut off from a piece of crystal in one operation.
The purpose of mechanical processing is to remove sawing undulations, to remove the surface layers which have been crystal-damaged by the relatively rough sawing processes or have been contaminated by the sawing wire and in particular to comprehensively level the semiconductor wafers. Surface grinding (single-side, double-side) and lapping are known in this respect, as are mechanical edge processing steps.
In single-side grinding, the back of the semiconductor wafer is held on a support (“chuck”) and the front is levelled by a cup wheel with the rotation of the chuck and grinding wheel and with a slow radial advance. Methods and devices for the surface grinding of a semiconductor wafer are known, for example from U.S. Pat. No. 3,905,162 and from U.S. Pat. No. 5,400,548 or from EP-0955126. In these documents, a semiconductor wafer is secured by one surface on a wafer holder, while the opposite surface is worked by a grinding wheel, in that the wafer holder and grinding wheel rotate and are pressed against one another. In this respect, the semiconductor wafer is attached on the wafer holder such that the centre thereof substantially coincides with the centre of rotation of the wafer holder. Furthermore, the grinding wheel is positioned such that the centre of rotation of the semiconductor wafer passes into a working region or into the peripheral region, formed by teeth, of the grinding wheel. As a result, the entire surface of the semiconductor wafer can be ground without any movement in the grinding plane.
In simultaneous double-side grinding (“double-disc grinding”, DDG), the semiconductor wafer is simultaneously worked on both sides in a free-floating manner between two grinding wheels which are mounted on opposite collinear spindles and is guided axially in a manner, substantially free from constraining forces, between a water cushion (hydrostatic principle) or air cushion (aerostatic principle) which acts on the front and on the back and is prevented from floating away in a radially loose manner by a surrounding thin guide ring or by individual radial spokes.
In lapping, the semiconductor wafers are moved under a specific pressure between an upper and a lower working wheel which mostly consist of steel and are usually provided with channels for an improved distribution of the abrasives, with the supply of a suspension (slurry) containing abrasive substances, as a result of which semiconductor material is removed.
DE 103 44 602 A1 and DE 10 2006 032 455 A1 describe methods for simultaneously grinding both sides of a plurality of semiconductor wafers with a sequence of movements similar to that of lapping, but they are characterised in that an abrasive is used which is firmly bound into working layers (“films, cloths”) applied onto the working wheels. A method of this type is termed “fine grinding with lap kinematics” or “planetary pad grinding” (PPG).
Working layers which are used in PPG and are bonded onto the two working wheels are described in, for example U.S. Pat. No. 6,007,407 A and U.S. Pat. No. 6,599,177 B2. During processing, the semiconductor wafers are introduced into thin guide cages, so-called runner wheels which have suitable openings for receiving the semiconductor wafers. The runner wheels have outer teeth which engage into a roll-off device consisting of an inner and an outer toothed ring and are moved by said roll-off device in the working gap formed between the upper and lower working wheel.
The edge of the semiconductor wafer including mechanical marks which may be present, such as an orientation notch, is usually also processed (edge rounding, “edge-notch-grinding”). Conventional grinding steps using profiled grinding wheels or belt grinding methods with continuous or periodic tool feed are used for this purpose. These edge rounding methods are used, since in the unworked state, the edge is particularly susceptible to breaking and the semiconductor wafer can be damaged by slight pressure and/or temperature loads in said edge region.
In a later processing step, the edge of the wafer which has been ground and treated with an etching medium is usually polished. In this respect, the edge of a centrally rotating semiconductor wafer is pressed against a centrally rotating polishing drum with a specific force (contact pressure). U.S. Pat. No. 5,989,105 discloses a method of this type for edge polishing in which the polishing drum consists of an aluminium alloy and is covered by a polishing cloth. The semiconductor wafer is usually fixed on a flat wafer holder, a so-called chuck. The edge of the semiconductor wafer projects over the chuck, so that it is freely accessible to the polishing drum.
The group of chemical processing steps usually includes wet-chemical cleaning and etching steps.
The group of chemo-mechanical processing steps includes polishing steps, by which the surface is smoothed partly by a chemical reaction and partly by a mechanical material removal (abrasion), and residual damage to the surface is removed.
Whereas single-side polishing methods (“single-side polishing”) usually result in relatively poor plane parallelisms, bilaterally engaging polishing methods (“double-side polishing”) produce semiconductor wafers with an improved evenness.
After the grinding, cleaning and etching steps, according to the prior art the surface of the semiconductor wafers is smoothed by strip polishing. In single-side polishing (SSP), the back of a semiconductor wafer is held on a support plate by putty, vacuum or by adhesion during processing. In double-side polishing (DSP), semiconductor wafers are introduced loosely into a thin toothed wheel and are polished simultaneously on the front and back, while they “float freely” between an upper and a lower polishing disc covered by a polishing cloth.
Furthermore, the fronts of the semiconductor wafers are often polished in a haze-free manner, for example with a soft polishing cloth using an alkaline polishing solution. In the literature, this step is often called CMP polishing (“chemo-mechanical polishing”). CMP methods are disclosed in, for example US 2002-0077039 and in US 2008-0305722.
Also known in the prior art are the so-called “fixed abrasive polishing” (FAP) technologies in which the silicon wafer is polished on a polishing cloth which contains an abrasive bound in the polishing cloth (“fixed-abrasive pad”). A polishing step in which an FAP polishing cloth of this type is used will be abbreviated in the following to an FAP step.
WO 99/55491 A1 describes a two-stage polishing method, with a first FAP polishing step and a subsequent second CMP polishing step. In CMP, the polishing cloth does not contain any bound abrasive. Here, as in a DSP step, abrasive is introduced as a suspension between the silicon wafer and the polishing cloth. A two-stage polishing method of this type is used in particular to remove scratches left behind on the polished surface of the substrate by the FAP step.
German patent application DE 102 007 035 266 A1 describes a method for polishing a substrate consisting of silicon material, the method comprising two FAP-type polishing steps which differ in that, in one polishing step, a polish suspension containing unbound abrasive as solids is introduced between the substrate and the polishing cloth, while in the second polishing step, a polish solution which is free from solids is used instead of the polish suspension.
Semiconductor wafers are often provided with an epitaxial layer, i.e. with a monocrystalline grown-on layer having the same crystal orientation, on which semiconductor components are applied at a later stage. Epitaxially coated or epitaxed semiconductor wafers of this type have particular advantages over semiconductor wafers consisting of homogeneous material, for example the prevention of a charge reversal in bipolar CMOS circuits followed by a short circuit of the component (“latch-up problem”), lower defect densities (for example a reduced number of COPs (“crystal-originated particles”) and the absence of a significant oxygen content, as a result of which the risk of a short circuit due to oxygen precipitates in component-relevant regions can be ruled out.
It is crucial how the previously described mechanical and chemo-mechanical or purely chemical procedural steps are ordered in a process sequence for the production of a semiconductor wafer.
It is known that the polishing steps such as SSP, DSP and CMP, the etching treatments and the epitaxy step produce a deterioration in the evenness of the semiconductor wafer, particularly in the peripheral region.
Therefore, attempts have been made in the prior art to keep the removal of material during polishing as low as possible to also keep the deterioration in the evenness to a minimum.
It is proposed in U.S. Pat. No. 5942445 A to separate a semiconductor wafer from the crystal (sawing), to round off the edge of the semiconductor wafer, to then carry out a grinding step which can comprise a double-side grinding and a single-side grinding of the front and back of the semiconductor wafer, to subject the semiconductor wafer to an alkaline wet etching procedure and finally to polish the semiconductor wafer by DSP. The double-side grinding can also be replaced by a lapping step. Plasma etching can also be carried out following the wet etching procedure. Finally, the grinding steps and the wet etching procedure can be replaced by plasma etching.
The semiconductor wafers which are polished by DSP and can be obtained by this method have an unsatisfactory shape in the peripheral region due to the use of wet-chemical treatments and to plasma-assisted chemical etching (PACE). Thus, semiconductor wafers with acceptable evenness values are at best available when a peripheral exclusion of at least 2 mm is always taken as a basis, cf. ITRS “Roadmap”. In particular, the nano-topology is adversely affected by etching processes. In order to improve the nano-topology after the etching step, in DSP an increased removal of material is necessary which in turn, however, adversely affects the shape in the peripheral region.
Other approaches are required in order to be able to provide semiconductor wafers for future technology generations, which wafers satisfy the high demands made on the edge region of the semiconductor wafer, thus for example to also make available the outermost peripheral region of the wafer to modern lithographic methods (immersion lithography).